All schematic level designs are done in virtuoso schematic design tool of Cadence IC 6.1.6 and executed in spectre simulator.
In this paper, an 8-bit segmented current-steering digital-to-analog converter (DAC) is presented where the digital and analog parts are unified using current mode binary to thermometer decoder, resulting in a smaller chip area and simple layout scheme.
In addition, the latch and driver circuits which are the main blocks of conventional current-steering DACs are eliminated in this design.
Finally, the proposed DAC is simulated in 0.18 μm CMOS technology with the 1.8 V supply voltage.
The post-layout simulation results show that differential nonlinearity and integral nonlinearity errors are 0.034 and 0.024 LSB, respectively.
The modified CS architecture is segmented as 6 4, to achieve optimum performance and to minimise area, where 6 most significant bits (MSBs) are realized using a unary sub-DAC and 4 least significant bits (LSBs) are implemented in Chinese abacus technique.
This proposed DAC consists of only three different types of current sources.
For further information, including about cookie settings, please read our Cookie Policy .
By continuing to use this site, you consent to the use of cookies.
We use cookies to offer you a better experience, personalize content, tailor advertising, provide social media features, and better understand the use of our services.
To learn more or modify/prevent the use of cookies, see our Cookie Policy and Privacy Policy.
Comments Current Steering Dac Thesis
Optimization techniques for decoding logic design in. - CiteSeerX
Has met the thesis requirements of Iowa State University. current steering DAC is dominated by the speed of the decoder circuits and the settling time.…
APPROACHES TO IMPROVE THE DYNAMIC CHARACTERISTICS.
The current-steering DAC is designed using binary weighted architecture. In this thesis, we have discussed different approaches to reach a high output.…
Area efficient D/A converter for accurate DC operation
This thesis acknowledges the following people for their support and assistance. Three different variations of a 3-bit current steering DAC are shown.…
A Cryogenic Current Steering DAC - UNSWorks
In this Masters thesis a low power high speed 10 bit current steering D/A converter is. Realization of partially segmented current steering DAC structure 30.…
Low Power 10-Bit DAC Design for Videoencoder - TUGraz digLIB
Sep 19, 2011. 3 The Architecture of Current Steering DACs in Detail. This thesis describes a low power 10bit digital to analog converter DAC designed for.…
DAC Linearization Techniques for Sigma-delta Modulators - OAKTrust
A Thesis by. AKSHAY GODBOLE. Submitted to the Office of Graduate Studies of. Texas A&M. and SQNR of a 4-bit current steering DAC is analyzed.…
Current-Steering DACs - SPIE
Current-Steering DACs. Current-steering DACs are a more common integrated DAC compared to resistor DACs. They are probably the most common bias.…
The Current-Steering DAC
Jan 31, 2018. binary-weighted DAC. We can also call it a current-switching—but not a current-steering—implementation. An important advantage of this.…
An 8-Bit Unified Segmented Current-Steering Digital-to-Analog.
Digital-to-analog converters, current-steering DAC has high speed. this structure with CMOS process, the current-steering DAC. dissertation, Thesis no. 667.…