Tags: Solving Problems With Linear EquationsWriting A Essay OnlineRainwater Harvesting Phd ThesisLeadership Essay RubricComputer Addiction Thesis PaperHsc Art Essay QuestionsCom 150 Effective Essay Writing
All schematic level designs are done in virtuoso schematic design tool of Cadence IC 6.1.6 and executed in spectre simulator.
In this paper, an 8-bit segmented current-steering digital-to-analog converter (DAC) is presented where the digital and analog parts are unified using current mode binary to thermometer decoder, resulting in a smaller chip area and simple layout scheme.
In addition, the latch and driver circuits which are the main blocks of conventional current-steering DACs are eliminated in this design.
Finally, the proposed DAC is simulated in 0.18 μm CMOS technology with the 1.8 V supply voltage.
The post-layout simulation results show that differential nonlinearity and integral nonlinearity errors are 0.034 and 0.024 LSB, respectively.
The modified CS architecture is segmented as 6 4, to achieve optimum performance and to minimise area, where 6 most significant bits (MSBs) are realized using a unary sub-DAC and 4 least significant bits (LSBs) are implemented in Chinese abacus technique.
This proposed DAC consists of only three different types of current sources.